My name is Lucas Castro, I am an undergraduate student at Unicamp - Campinas/SP - Brasil. I am developing an undergraduate project involving RISC-V, named ReonV, under supervision of professor Rodolfo Azevedo ( https://www.ic.unicamp.br/~rodolfo/ ) financed by Fapesp ( http://www.fapesp.br/ ) and I would like to announce it here.

Our ideia was to propose a way of avoiding compatibility problems when developing Hardware (processors, in this case) reusing well consolidated Open or Free Hardware. For example, every time a new RISC-V processor project begins, it has to develop the processor, build it's own support to every board it is meant to run, use strictly the tools used to develop it and create support to every peripheral. Trying to expand the support is not trivial. 

We took a different approach with ReonV. We used a well consolidated processor, Leon3 provided as part of the GRLIB IP Library on GPL license by Cobham Gaisler AB which has SPARC ISA, with support to many boards, synthesis tools, peripherals and entirely customizable and only changed it's ISA to RISC-V. This way we gain a RISC-V processor with all the previous support Leon3 already had without having to rebuild it to our own project. 

We currently have a RV32I processor with no special and fence instructions capable of running some test programs. We are currently working on making a console available and running benchmarks.

The project repository has been just opened, it is released under GPL and can be found here: https://github.com/lcbcFoo/ReonV

There are a lot of things to be done, issues related to tools developed for SPARC and being used to RISC-V with workarounds and boards to test (unfortunately we only have nexys4ddr e zedboard to test the project). We really would appreciate suggestions, commentaries, opinions or anything you can offer related to ReonV =)